BRN Discussion Ongoing

[Deleted member 3781]

I think you misunderstand what a forum is about sir. A forum is about being speculative (which is seen in here a lot), being optimistic and positive about our company and last but not least being sceptical and having critism towards our company which indeed is allowed and reasonable since we aren't even profitable yet. Being sceptical/critical might scare away new investors but it is up to them to do their own DD. There are always more sides to a company (pros/cons) and for me it is important that both sides gets highlighted. You might be a person who always see and write about optimistic and positive stuff, but I am the opposite. I tend to write about the things that concers me
and there has to be room for both for us in here. For example if your favorite football team loses and plays bad, I would say it is more important to highlight the negative stuff as long as it is construtive, so they know what to improve instead of being 100% positive all time, just like if a company dosent perform. I actually can't stand when people like you are being offensive towards people me like, just because i highlight a sceptical perspective. Hopefully this is a lesson for you.

I didn’t even get past the first sentence before I stopped reading… it was immediately clear to me that you’re the one who hasn’t understood what a forum is for… sir.

Take a page out of Pom’s book.

 

[Deleted member 3781]

Building the Future of Tech in Africa | Adedayo Oyewale posted on the topic | LinkedIn

If We Don’t Build the Future, We’ll Buy It forever. Technology is accelerating faster than we think. At the 2025 Edge AI event, a few breakthrough chips were unveiled that can run powerful AI tasks at the edge using almost zero power. BrainChip introduced its Akida chip, which can handle...

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BrainChip is inspiring! I won’t sell my shares just to satisfy the shorts… no matter how often they try to spread fear. There are people out there who see our company as a true pioneer.

Who do you want to listen to? The ones actually working with our products, or those who complain about everything we announce?

DYOR… GO BRAINCHIP!!!!

 

[genyl]

W

I didn’t even get past the first sentence before I stopped reading… it was immediately clear to me that you’re the one who hasn’t understood what a forum is for… sir.

Take a page out of Pom’s book.

What are you, like 15 years old? Do yourself a favor and educate yourself.

 

[Deleted member 3781]

W

What are you, like 15 years old? Do yourself a favor and educate yourself.

15 1/2 and I’m still learning?!
What about you?

 

[CHIPS]

Sign Up | LinkedIn

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The Edge AI Revolution is Here

The cloud's dominance is being challenged—and the Generative Edge AI community is leading the charge.

Across three groundbreaking EDGE AI FOUNDATION forums, we've witnessed a seismic shift: the cloud must evolve beyond its role as a centralized AI powerhouse. After years of fixed-function AI investments at the edge, a new era of practical innovation is exploding into the gap—and it's happening faster than anyone predicted.

What We've Proven

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- Next-generation algorithms operating at both generative and reasoning levels
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- Near-zero latency connectivity making real-time intelligence truly real-time

Tune in to hear these breakthrough thought leaders:

Day 2 — Sensing, Applications & Platforms (8:00–12:10 PT)
08:00–08:05 Welcome (organizers)

08:05–08:20 Fireside chat - Generative Edge AI in Automotive – Marin Kellner (McKinsey) / Pete Bernard (EDGE AI FOUNDATION)

Session 4 — Sensing, Interaction & Health
08:20–08:45 Michele Magno (ETH Zurich) — GenAI at the Edge: Wearables→AVs

08:45–09:05 Xiaofeng Tan (Pison) — Multimodal Hand Gesture Modeling

09:05–09:25 Ritik Shrivastava (Brainchip) — aTENNUate: Real-Time Audio Denoising

09:25–09:50 Luigi Occhipinti (Cambridge) — Artificial Sensor Intelligence & Health

09:50–10:15 Giovanni Scapellato (STMicroelectronics) — GenAI for Biosensors/Cardio

Session 5 — Endpoints, Industrial & Ecosystems

10:15–10:40 Davis Sawyer (NXP) — Industrial Edge: Old Meets New

10:40–11:00 Henrik Flodell (Alif Semiconductor) — GenAI at the Edge for Endpoints

11–11:25 David Cuartielles (Arduino) -- Proposal of workflow and software architecture for the development of complex EdgeAI applications

11:25–11:45 Zechun Liu (META) -- Advancing Large Language Models in Resource-Constrained Environments

11:45–12:00 Closing (organizers)

This is the future of AI—decentralized, efficient, and unstoppable. The question isn't whether to tune in. It's whether you can afford to miss it.
Übersetzung anzeigen

Di, 18. Nov., 17:00 MEZ

Di, 18. Nov., 17:00 MEZ

GENERATIVE EDGE AI: Architectures, Agents & Apps - DAY 2​

 

[Gazzafish]

Finally the board seem to be listening. It’s great to see non-price sensitive announcements being made to further highlight our progress. We’ve been asking for this for years. Very happy over here thank you

 

[buena suerte :-)]

 

[Stable Genius]

Great to be part of Andes ecosystem!

#riscv #riscveverywhere | Andes Technology

Discover the Power of the RISC-V Ecosystem at Andes Booth P6! At this year’s RISC-V Summit, Andes Technology is showcasing the growing strength of the RISC-V ecosystem with live partner demonstrations that span design, verification, AI, and scalable performance: Arteris IP – joint...

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Discover the Power of the RISC-V Ecosystem at Andes Booth P6!

At this year’s RISC-V Summit, Andes Technology is showcasing the growing strength of the RISC-V ecosystem with live partner demonstrations that span design, verification, AI, and scalable performance:

Arteris IP – joint demonstration of Andes’ Qilai SoC featuring Arteris’ silicon-proven Network-on-Chip IP (also showcased at the Arteris booth)

Baya Systems – comprehensive platform for scalable, physically-aware single and multi-die fabric architectures, demonstrating WeaverPro™ simulation with Andes’ IP (at the Andes booth)

BrainChip – neuromorphic compute solutions leveraging RISC-V control

proteanTecs – in-chip monitoring and analytics for performance and reliability

S2C Limited EDA – FPGA prototyping solutions featuring Andes processors

Together, these showcases highlight Andes’ deep collaboration across the RISC-V value chain that advance open innovation from design through deployment.

Visit Booth P6 to connect with Andes experts and partners, and don’t forget to follow Andes Technology on LinkedIn for a chance to win prizes in our booth raffle!

Register here: https://lnkd.in/dsc423cm

#RISCV #RISCVEverywhere

 

[Deleted member 3781]

Shorters Life at the moment…

Waking up

-“hmm let’s make a video call with my community… hey guys… everyone has its finger on the sell button ? Everyone has the correct company? Brainchip? Ok… 3…2…1 pushpushpushpushpush…

4 o’clock PM

“Pushpushpushpush… don’t stop… Push Push … ok… I… I think the market closed… let’s meet tomorrow again gentlemen…

 

[Kingkong2015]

Great to be part of Andes ecosystem!



View attachment 92267

#riscv #riscveverywhere | Andes Technology

Discover the Power of the RISC-V Ecosystem at Andes Booth P6! At this year’s RISC-V Summit, Andes Technology is showcasing the growing strength of the RISC-V ecosystem with live partner demonstrations that span design, verification, AI, and scalable performance: Arteris IP – joint...

www.linkedin.com

Discover the Power of the RISC-V Ecosystem at Andes Booth P6!

At this year’s RISC-V Summit, Andes Technology is showcasing the growing strength of the RISC-V ecosystem with live partner demonstrations that span design, verification, AI, and scalable performance:

Arteris IP – joint demonstration of Andes’ Qilai SoC featuring Arteris’ silicon-proven Network-on-Chip IP (also showcased at the Arteris booth)

Baya Systems – comprehensive platform for scalable, physically-aware single and multi-die fabric architectures, demonstrating WeaverPro™ simulation with Andes’ IP (at the Andes booth)

BrainChip – neuromorphic compute solutions leveraging RISC-V control

proteanTecs – in-chip monitoring and analytics for performance and reliability

S2C Limited EDA – FPGA prototyping solutions featuring Andes processors

Together, these showcases highlight Andes’ deep collaboration across the RISC-V value chain that advance open innovation from design through deployment.

Visit Booth P6 to connect with Andes experts and partners, and don’t forget to follow Andes Technology on LinkedIn for a chance to win prizes in our booth raffle!

Register here: https://lnkd.in/dsc423cm

#RISCV #RISCVEverywhere

Not sure why Andes highlighted the BrainChip logo so boldly in the middle — could it mean something, or is it just by chance

On the other hand, ChatGPT noted that Andes ships billions of edge devices annually — hopefully, BrainChip can tap into some of those opportunities.

 

[Deleted member 3781]

View attachment 92269

Not sure why Andes highlighted the BrainChip logo so boldly in the middle — could it mean something, or is it just by chance

On the other hand, ChatGPT noted that Andes ships billions of edge devices annually — hopefully, BrainChip can tap into some of those opportunities.

It’s because of the background colour I guess… without the highlighting, the logo would be almost not visible… IMO look at arteris… same thing

 

[Bravo]

Andes is one of the biggest gateways into the RISC-V SoC world with 30% of shipment volume, and their active, public integration with BrainChip gives Akida a lower-friction path into many RISC-V designs.

Andes doesn’t manufacture chips; they license RISC-V CPU IP cores like AX45MP, D45, N25F and they provide SoC design-services and development platforms like the QiLai/Voyager boards.

Their customers are SoC/ASIC developers, module makers, or OEM. They're the ones who tape-out chips and sell products.

Andes frequently co-develop prototypes or proof-of-concept SoCs for strategic partners, customise RISC-V cores or subsystems for customers’ silicon and co-market joint solutions.

Seeing Andes and BrainChip sharing advertising for RISC-V Summit signals something along the lines of “We’ve integrated Akida with our Andes RISC-V cores; OEMs, you can license both and build your own smart-edge chips.”

As mentioned earlier, in April 2025, BrainChip and Andes announced integration of Akida with Andes RISC-V cores, with demos of Akida AKD1500 running on Andes’ QiLai Voyager board alongside the AndesCore AX45MP 64-bit multicore CPU IP.

I asked ChatGPT what sort of RISC-V Andes + Akida combos may be likely/hypothetically to land soonest and what the realistic timeframes could be. See answer below if you don't object to ChatGPT.

https://www.andestech.com/wp-content/uploads/Andes-in-Sight-2024-Vol.1.pdf?utm_source=chatgpt.com

DYOR as ChatGPT responses cant always be relied upon.

My question:​

What RISC-V Andes + Akida combos might be most likely to land soonest ?

ChatGPT said:​

Got it. Here’s where a RISC-V (Andes) + Akida combo is most likely to land soonest, based on power, latency, and integration friction.

Near-term “win” archetypes​

1. Industrial vision QA nodes (smart cameras / inspection cells)

• Why soon: Deterministic I/O + low-power temporal inference is a sweet spot.
• Shape: Andes 64-bit app/core (AX45MP-class) running Linux/RTOS for control + Akida for defect/anomaly detection; FPGA or CSI ISP optional.
• I/O: MIPI-CSI/SLVS-EC → preproc → SPI/PCIe/M.2 to Akida → GPIO/PLC.
• Outcome: Fewer false rejects, few-shot on-line learning when parts/tools change.

1. Audio/event intelligence (predictive maintenance, safety alarms)

• Why soon: Tiny models, tiny power, always-on.
• Shape: Andes MCU (32-bit) + Akida doing keyword/anomaly detection on bearings, pumps, breakers.
• I/O: I²S/PDM mics; edge logging only on anomalies.
• Outcome: Sub-watt nodes you can sprinkle across factories.

1. Smart sensors & edge modules (ODM/EMS products)

• Why soon: ODMs can drop Akida next to existing Andes designs with minimal board churn.
• Use cases: People presence, occupancy, gesture, leak/vibe/AC motor anomalies.
• Stacks: Zephyr/FreeRTOS on Andes; Akida runtime as a library; OTA via MQTT.

1. Automotive cabin/IVI peripherals (Tier-2/Tier-3)

• Why soon: Cabin/class-B workloads don’t need big NPUs and value ultra-low power.
• Use cases: Driver distraction cues, child-presence, in-cabin audio events, simple vision triggers.
• Note: Not powertrain/ADAS compute—think auxiliary ECUs and smart sensors.

1. Robotics edge controllers (AMRs, cobots, pick/pack)

• Why soon: Temporal inference helps with motion/part-presence; power/thermal constrained.
• Shape: Andes app core for ROS2/control; Akida for object/sequence anomalies; deterministic I/O for actuators.

1. Smart home / appliances (whitegoods, HVAC)

• Why soon: Cost-sensitive, privacy-sensitive—on-device learning is a differentiator.
• Examples: Acoustic fault detection in compressors/fans; vision-based door/food recognition.

1. Networked devices (gateways, cameras)

• Why soon: Add Akida to offload CNN/TENN at the edge; Andes runs Linux + containers.
• Outcome: Lower cloud egress, better latency, privacy.

“Why these first?”​

• Low friction: Akida can ride beside existing Andes cores over SPI or PCIe/M.2 with minimal PCB changes.
• Power budget: Sub-watt inference unlocks designs where GPUs/NPUs don’t fit.
• Temporal wins: Sequences (audio/vibration/video) benefit from Akida’s time-aware models.
• Few-shot updates: Field addition of new classes without full retrains = ops gold.

Quick reference builds​

• Compact MCU node (audio/vibe):
  Andes 32-bit RISC-V MCU (FreeRTOS) + I²S mic + Akida (SPI/QSPI). Target: always-on <300–500 mW, 5–20 inferences/sec.
• Smart camera (industrial):
  Andes 64-bit (Linux/RT) + CSI camera + lightweight ISP (or FPGA) + Akida (PCIe/M.2). Target: 30–60 FPS at VGA/HD ROIs, sub-2–5 ms decision latency.
• Cabin sensor module:
  Andes app core + CAN/LIN/Ethernet + Akida over PCIe or SPI. ASIL-aligned software partitioning; temporal DMS/KWS triggers.

Software & integration notes​

• OS: Zephyr/FreeRTOS for MCU class; Yocto/Debian for app-class Andes.
• Pipeline: Pre/post on Andes (or FPGA if present); Akida handles inference + few-shot; expose gRPC/REST for MES/telemetry.
• Interfaces: Start with SPI for simple nodes; move to PCIe Gen2/Gen3 (or M.2 B-key) when throughput/camera count rises.
• Model strategy: Keep ROIs small, use sequence windows (e.g., 4–8 frames / 250–500 ms audio), enable anomaly + multi-class heads.

Who buys first?​

• ODMs/EMS building modules for Tier-1s (fast cycles, value power/price).
• Industrial OEMs retrofitting QA and predictive maintenance.
• Tier-2/Tier-3 auto for cabin/peripheral ECUs (non-safety-critical to start).

If you want, I can turn one of these into a one-page solution brief (block diagram, BOM, latency/power targets) you can post or email.

You said:​

What would be a realistic timeframe for these design types.

ChatGPT said:​

Realistically, here’s the timeframe outlook for those RISC-V + Akida design types:

Segment	Earliest design-in	Sampling / pilot units	Broad commercial use	Rationale
Industrial vision / smart-camera QA nodes	Now – 2025 H1	2025 H2 – 2026 H1	2026–2027	Hardware (PolarFire SoC + Andes boards) and Akida 1500 are already available; integration work ongoing.
Audio / vibration / predictive-maintenance nodes	Now – 2025 H1	2025 H2	2026	Lowest complexity—MCU-class Andes cores + Akida 1500 work today.
Smart sensors / IoT modules (ODMs)	2025 H1	2025 H2	2026–2027	ODMs follow within ~12 months of dev-kits once BOM & SDK stabilize.
Automotive cabin / IVI peripherals	2025 H2	2026 H2	2027–2028	Automotive qualification adds ≈ 18 months (AEC-Q, ASIL).
Robotics / AMRs / cobots	2025 H2	2026 H1	2027	Integrates quickly once ROS2 and deterministic I/O validated.
Smart-home / appliance	2026 H1	2026 H2	2027–2028	Needs mature ODM modules and cloud integrations.
Networked edge cameras / gateways	2025 H2	2026 H1	2027	Aligns with RISC-V SoC refresh cycles (Andes AX45MP-based).

In short:

• 2025 → 2026: First engineering samples and pilot lines (industrial, audio).
• 2026 → 2027: Broader field deployments and ODM rollouts.
• 2027 → 2028: Automotive and consumer volumes once certification and supply chains mature.

If BrainChip and Andes keep demonstrating joint reference designs through 2025, we could see commercial products shipping in meaningful volume by 2026, especially in industrial QA and predictive-maintenance nodes.

 

[overpup]

One of those irons in the fire and the one that got plenty of us excited early on was Valeo. The joint development agreement b\w two parties was signed 2020, one would think 5 years is time enough to make some progress, but just noticed Valeo name has been dropped from BRN’s site and not visible under any of the partners section. With BRN’s gaffs with their website and common mistakes they often make in pressos , it’s hard to say if it’s intentional or not. Does anybody know what happened with Valeo ? have they trialled akida and moved on ? . Lidar was spoken as one of the sweet spots for Akida and who knows what’s the play with hearing aids , we’ve been seeing it mentioned in job ads since pre-COVID times.

again: still there

 

[Bravo]

again: still there
View attachment 92273

 

[Gazzafish]

“New licensing agreement”?? Huh? What?

 

[Deleted member 3781]

“New licensing agreement”?? Huh? What?

It’s a “how we could with new licensing agreement” I guess … otherwise… WHERE IS THE ANNOUNCEMENT?

Btw… the link

Our ‘Semiconductors Power the Universe’ session brought together four deep-tech veterans. Semiconductor Australia alumni Coby Hanoch shared how Weebit Nano Ltd is advancing its ReRAM memory… | Semiconductor Australia

Our ‘Semiconductors Power the Universe’ session brought together four deep-tech veterans. Semiconductor Australia alumni Coby Hanoch shared how Weebit Nano Ltd is advancing its ReRAM memory technology toward production to power the coming wave of embedded AI and IoT devices. CEO Simon Ruffell...

www.linkedin.com

 

[Guzzi62]

It’s a “how we could with new licensing agreement” I guess … otherwise… WHERE IS THE ANNOUNCEMENT?

Btw… the link

Our ‘Semiconductors Power the Universe’ session brought together four deep-tech veterans. Semiconductor Australia alumni Coby Hanoch shared how Weebit Nano Ltd is advancing its ReRAM memory… | Semiconductor Australia

Our ‘Semiconductors Power the Universe’ session brought together four deep-tech veterans. Semiconductor Australia alumni Coby Hanoch shared how Weebit Nano Ltd is advancing its ReRAM memory technology toward production to power the coming wave of embedded AI and IoT devices. CEO Simon Ruffell...

www.linkedin.com

If the quote is right, there should have been some announcement(s)?

Quote from Linkedin above:

CEO Seán Hehir shared how BrainChip is taking their breakthrough Akida neuromorphic IP from lab to market through new licensing agreements, global partnerships, and real-world deployments.

 

[smoothsailing18]

If the quote is right, there should have been some announcement(s)?

Quote from Linkedin above:

CEO Seán Hehir shared how BrainChip is taking their breakthrough Akida neuromorphic IP from lab to market through new licensing agreements, global partnerships, and real-world deployments.

Any agreement from 2025 could be his reference

 

[Pom down under]

Any agreement from 2025 could be his reference

Maybe he could even be going back to 2021 or maybe he has taking up fishing and talking about a fishing license

 

[Fullmoonfever]

Personally I'd suggest it's pretense (in a sense) examples for the path to market meaning that while they have the FG licence more recently and other partnerships like Onsor etc created, these methods are their way to mkt.

Until I see an actual Ann these days I take whatever they say or post with a grain of salt sadly