BRN Discussion Ongoing

[itsol4605]

Over 14,000 hits since released in 6 hours, something BRN should do in its next breakthrough.
Great marketing example

A big announcement...
...and then all you hear about are the many problems that still need to be solved.

Problems that BrainChip has long since solved.

I'm glad she's talking about a competitor!

14,000 clicks – interest in neuromorphic computing is increasing significantly!

 

[Tothemoon24]

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Link

aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on Raw Audio

Sean did mention hearing aids sometime ago , hopefully another step or perhaps a leap has been made towards another of Sean’s comments

“ the financials “

 

[smoothsailing18]

A big announcement...
...and then all you hear about are the many problems that still need to be solved.

Problems that BrainChip has long since solved.

I'm glad she's talking about a competitor!

14,000 clicks – interest in neuromorphic computing is increasing significantly!

I agree, altho my point is referring to having this type of tool meaning , video used as a social media marketing for BRN.

 

[Frangipani]

Less than two months ago, our then Regional Sales Manager in Taiwan, Edward Lien (who just announced that he had left our company) posted on LinkedIn that he were looking forward to attending 2025 Andes RISC-V CON Beijing:

I assume he was originally also scheduled to be the speaker representing BrainChip at that conference, which will take place on 27 August:

ANDES RISC-V CON Beijing | EventX

AI 与车用科技快速演进，推动业界对高效运算与资安技术的高度需求。 RISC-V 凭借其开放、弹性与可扩充架构，正成为高性能运算领域的关键解决方案。

spot.eventx.io

If you had checked out the conference website over the past few days, you would have been greeted with this (screenshot taken on 6 August):

Earlier today, I noticed that the BrainChip logo has now been replaced with a photo of what appears to be a new Taipei-based hire called Jerry Kuo, who is described as a Solutions Architect at BrainChip.

This new position is, however, not yet reflected in what I believe to be his LinkedIn profile (despite not listing MediaTek as a former employer):

https://www.linkedin.com/in/jerry-kuo-1294719/

 

[Frangipani]

Another fairly new employee - but based in the US - is Thang Pham, a Digital Design Engineer, who is concurrently working (now part-time) as a postdoc at BrainChip’s partner university ASU (Arizona State University). He holds a PhD in Electrical and Computer Engineering “with specialized expertise in digital IC design, spanning the ASIC flow from specification and architecture, RTL design, verification, to tape-out, and FPGA prototyping.”

https://www.linkedin.com/in/thang-pham-a17347288

 

[Frangipani]

Akida gets a fleeting mention in the context of neuromorphic chips in a newly published paper by researchers from the University of Pisa and ESA’s ESTEC (European Space Research and Technology Centre) titled “Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review”:

🚀 Excited to share that my latest peer-reviewed article — "Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review" — has just been published! | Gabriela Mystkowska

🚀 Excited to share that my latest peer-reviewed article — "Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review" — has just been published! 📝 In this work, we present a comprehensive state-of-the-art review of hardware architectures for AI on-the-edge in space missions...

www.linkedin.com

https://ieeexplore.ieee.org/ielx8/6287639/6514899/11115053.pdf?

(…)

(…)

(…)

Disappointingly, Akida is only mentioned once in context with the Mercedes-Benz Vision EQXX concept car (p.10) but neither as an example of neuromorphic hardware supporting on-chip learning (p.10) nor in context with Frontgrade Gaisler’s NEUROSPACE project (which is part of OSIP, ESA’s Open Space Innovation Platform, p.11) nor in connection with ANT61 (p.11, here the co-authors also failed to follow up on the launched satellite’s fate).

By the way: If you thought “Edge AI for Space Applications” were more or less synonymous with “Neuromorphic Edge AI” - think again and have a closer look at the paper…

It does, however, end on a positive future outlook for neuromorphic computing in space applications:

“The emerging neuromorphic computing represents a promising approach for on-chip learning, which may help to increase the accuracy and shorten model development. Using SNNs might be essential in autonomous deep space missions which have very constrained telecommunication capabilities.

Hardware is not the only crucial part of AI success in space: the reliability of AI algorithms, model training, and other obstacles, which have not been mentioned in this article, have a great impact on the successful deployment of AI algorithms in space applications.”

 

[Diogenese]

View attachment 89687
FPGA Roundtable: Golden Dome Architecture – Accelerating Multi-Domain Defense

August 28 | 2 PM ET | Virtual Event
Hosted with Military Embedded Systems
Speed. Adaptability. Secure, real-time decisions.

Join four leaders driving the next wave of defense innovation as they explore how FPGA architectures are transforming multi-domain operations.

Why Attend?
It’s not just about technology — it’s about aligning speed, adaptability, and secure decision-making to meet the demands of the modern battlespace. Our experts will show you how FPGA innovation is making it possible.

FPGA Roundtable: Golden Dome Architecture – Accelerating Multi-Domain Defense

August 28 | 2 PM ET | Virtual Event
Hosted with Military Embedded Systems
Speed. Adaptability. Secure, real-time decisions.

Join four leaders driving the next wave of defense innovation as they explore how FPGA architectures are transforming multi-domain operations.

Why Attend?
It’s not just about technology — it’s about aligning speed, adaptability, and secure decision-making to meet the demands of the modern battlespace. Our experts will show you how FPGA innovation is making it possible.

View attachment 89688

FPGAs are used for demonstrations and short run production which does not raise to the level of ASIC wafer production.

An individual FPGA chip would be more expensive than an individual ASIC chip.

 

[Diogenese]

Again, please look at the PDF, which can be downloaded. It is too large to post here, but it mentions Akida 42 times!

https://www.researchgate.net/publication/393922950_Quantization-Aware_Neuromorphic_Architecture_for_Efficient_Skin_Disease_Classification_on_Resource-Constrained_Devices

View attachment 89684



View attachment 89685

Just an abstract:
View attachment 89686

"A beautiful set of numbers"

 

[Diogenese]

Interesting !!

1000 analog neurons!!!

... plus a digital spiking fabric

... plus a CNN accelerator????

 

[Diogenese]

Meanwhile, somewhere in Alaska:

Person 1: "Do you want to stop killing people?"

Person 2: "We have all the videos, Donald. "

Person 1: "Would you like some rare earths?"

 

[HopalongPetrovski]

1000 analog neurons!!!

... plus a digital spiking fabric

... plus a CNN accelerator????




View attachment 89717

Hi Dio.
How do you rate this as direct competition for our markets?
i.e. Are they cutting our lunch or just cutting the cheese?

 

[Diogenese]

Hi Dio.
How do you rate this as direct competition for our markets?
i.e. Are they cutting our lunch or just cutting the cheese?

Hi Hoppy,

Without the performance figures, it's hard to make a dir3ect comparison.

Pulsar sprang Phoenix-like from the ashes of analog SNN research, only they have not dusted off the dying embers.

It seems to me that the Innatera chip would involve more manufacturing steps, even a couple of different manufacturing processes? This would make the chip more expensive to make.

https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.202500203

A problem with ReRAM is the performance varies from element to element, and this necessitates remedial processing/circuitry. This reduces the theoretical advantages of analog v digital.

This Innatera patent application illustrates the complications:

EP4548260A1 CALIBRATION OF SPIKING NEURAL NETWORKS 20220629

[0006] Analog and mixed signal circuits, typically fabricated as an integrated circuit, are a power-efficient way to implement SNNs. One drawback of analog signal processing circuits is that their performance can vary with manufacturing tolerances as well as environmental factors like temperature and supply voltage variations. Digitally assisted analog-mixed signal circuits can be used as an alternative to provide reliable performance. The amount of assistance needs to be bounded and optimized.
...
[0011] To perform such an improved calibration procedure, circuit parameters may be measured and subsequently adjusted to conform to predefined specifications. In complex analog and mixed signal networks it may not be practical to directly measure all relevant parameters with sufficient accuracy, necessitating a calibration strategy that makes optimal use of observable parameters to deduce values for non-observable parameters. Relevant circuit parameters should be made adjustable with sufficient range to overcome expected variability and sufficient resolution to achieve the predefined specifications. [0012] Due to the complexity of the SNN and the varied kind of components used in the design of an analog or mixed signal SNN system-on-a-chip (SoC), the optimal trade-off between performance versus the amount of calibration under the SoC constraints is a nontrivial problem. This invention provides a system and method for such calibration in an SNN with varied components, connectivity and limited observability and measurability.
... the SNN comprises a plurality of input processing circuits, each input processing circuit having an input for receiving a spiking neural network input signal and being configured to apply a transfer function to the input signal to generate a processed input signal;
a plurality of offset current generators, each offset current generator configured to generate an offset current signal at a predetermined level;
a plurality of synapses, each synapse connected to receive a processed input signal from one of the input processing circuits and configured to apply a predetermined weight to the processed input signal to generate a synapse output signal;
a plurality of neurons, each neuron connected to receive synapse output signals from a subset of the synapses and an offset current signal from one of the offset current generators, and each neuron configured to generate a neuron output signal in response to the received synapse output signals and offset current signal; and
an analog-to-digital converter having an input, the input being connectable to receive an offset current signal from one of the offset current generators, and being configured to convert the received offset current signal to a corresponding digital output signal.

They have to tweak each individual ReRAM circuit to bring its performance within spec.

The analog SNN (1k elements) might serve as an always on movement detector, or possibly KWS to wake up the rest of the chip processors. We have Pico to do this, and Akida is multifunctional and can serve this purpose with a few NPUs while leaving the rest of the NPUs free for other tasks.



Innatera bill Pulsar as "Pulsar: The first commercially available, brain-inspired microcontroller for sensing at the edge".
https://innatera.com/pulsar

 

[HopalongPetrovski]

Hi Hoppy,

Without the performance figures, it's hard to make a dir3ect comparison.

Pulsar sprang Phoenix-like from the ashes of analog SNN research, only they have not dusted off the dying embers.

It seems to me that the Innatera chip would involve more manufacturing steps, even a couple of different manufacturing processes? This would make the chip more expensive to make.

https://advanced.onlinelibrary.wiley.com/doi/10.1002/aelm.202500203

A problem with ReRAM is the performance varies from element to element, and this necessitates remedial processing/circuitry. This reduces the theoretical advantages of analog v digital.

This Innatera patent application illustrates the complications:

EP4548260A1 CALIBRATION OF SPIKING NEURAL NETWORKS 20220629

[0006] Analog and mixed signal circuits, typically fabricated as an integrated circuit, are a power-efficient way to implement SNNs. One drawback of analog signal processing circuits is that their performance can vary with manufacturing tolerances as well as environmental factors like temperature and supply voltage variations. Digitally assisted analog-mixed signal circuits can be used as an alternative to provide reliable performance. The amount of assistance needs to be bounded and optimized.
...
[0011] To perform such an improved calibration procedure, circuit parameters may be measured and subsequently adjusted to conform to predefined specifications. In complex analog and mixed signal networks it may not be practical to directly measure all relevant parameters with sufficient accuracy, necessitating a calibration strategy that makes optimal use of observable parameters to deduce values for non-observable parameters. Relevant circuit parameters should be made adjustable with sufficient range to overcome expected variability and sufficient resolution to achieve the predefined specifications. [0012] Due to the complexity of the SNN and the varied kind of components used in the design of an analog or mixed signal SNN system-on-a-chip (SoC), the optimal trade-off between performance versus the amount of calibration under the SoC constraints is a nontrivial problem. This invention provides a system and method for such calibration in an SNN with varied components, connectivity and limited observability and measurability.
... the SNN comprises a plurality of input processing circuits, each input processing circuit having an input for receiving a spiking neural network input signal and being configured to apply a transfer function to the input signal to generate a processed input signal;
a plurality of offset current generators, each offset current generator configured to generate an offset current signal at a predetermined level;
a plurality of synapses, each synapse connected to receive a processed input signal from one of the input processing circuits and configured to apply a predetermined weight to the processed input signal to generate a synapse output signal;
a plurality of neurons, each neuron connected to receive synapse output signals from a subset of the synapses and an offset current signal from one of the offset current generators, and each neuron configured to generate a neuron output signal in response to the received synapse output signals and offset current signal; and
an analog-to-digital converter having an input, the input being connectable to receive an offset current signal from one of the offset current generators, and being configured to convert the received offset current signal to a corresponding digital output signal.

They have to tweak each individual ReRAM circuit to bring its performance within spec.

The analog SNN (1k elements) might serve as an always on movement detector, or possibly KWS to wake up the rest of the chip processors. We have Pico to do this, and Akida is multifunctional and can serve this purpose with a few NPUs while leaving the rest of the NPUs free for other tasks.



Innatera bill Pulsar as "Pulsar: The first commercially available, brain-inspired microcontroller for sensing at the edge".
https://innatera.com/pulsar

Hi Dio.
Thank you for your reply.
Anastasia did bring up the problem regarding scaling of the 1000 analogue neurones component and the whole thing looks a little Frankenstein with the stitched on digital fabric and cnn accelerator, but, its apparently available now and is targeting our specific markets using our sales rhetoric.
At the very least, muddying the waters.
I guess it will come down to reliability, actual availability, ease of implementation and cost.
It certainly doesn't hurt their side of the ledger having a babe spruiking their product.
As someone said earlier, good marketing.

 

[Rach2512]

Sorry if already posted.


Edge AI and Agentic AI: Pioneering the Future of Autonomous Intelligence https://www.linkedin.com/pulse/edge-ai-agentic-pioneering-future-autonomous-madhu-gaganam-lfb2c

 

[CHIPS]

Akida gets a fleeting mention in the context of neuromorphic chips in a newly published paper by researchers from the University of Pisa and ESA’s ESTEC (European Space Research and Technology Centre) titled “Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review”:

🚀 Excited to share that my latest peer-reviewed article — "Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review" — has just been published! | Gabriela Mystkowska

🚀 Excited to share that my latest peer-reviewed article — "Hardware Platforms Enabling Edge AI for Space Applications: A Critical Review" — has just been published! 📝 In this work, we present a comprehensive state-of-the-art review of hardware architectures for AI on-the-edge in space missions...

www.linkedin.com

View attachment 89702

https://ieeexplore.ieee.org/ielx8/6287639/6514899/11115053.pdf?

View attachment 89703

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Disappointingly, Akida is only mentioned once in context with the Mercedes-Benz Vision EQXX concept car (p.10) but neither as an example of neuromorphic hardware supporting on-chip learning (p.10) nor in context with Frontgrade Gaisler’s NEUROSPACE project (which is part of OSIP, ESA’s Open Space Innovation Platform, p.11) nor in connection with ANT61 (p.11, here the co-authors also failed to follow up on the launched satellite’s fate).

By the way: If you thought “Edge AI for Space Applications” were more or less synonymous with “Neuromorphic Edge AI” - think again and have a closer look at the paper…

It does, however, end on a positive future outlook for neuromorphic computing in space applications:

“The emerging neuromorphic computing represents a promising approach for on-chip learning, which may help to increase the accuracy and shorten model development. Using SNNs might be essential in autonomous deep space missions which have very constrained telecommunication capabilities.

Hardware is not the only crucial part of AI success in space: the reliability of AI algorithms, model training, and other obstacles, which have not been mentioned in this article, have a great impact on the successful deployment of AI algorithms in space applications.”

I remember having seen Gabriela Mystkowska in a photo taken in the BrainChip private room at some trade fair. She was part of a group visiting BrainChip. I can't remember the other people, though. As far as I remember, the picture was marked as "our partners XX" and changed or deleted later, probably because of the mistake that she was not part of the partner group.

But maybe I am mistaken, maybe it was some other lady, though I immediately remembered her when I saw this photo.

 

[IloveLamp]

US Space Force's new deep space radar tracks multiple satellites 22,000 miles away in key test | Space https://share.google/OMepwxScqnJUwa4tO

 

[supersonic001]

Congratulations to SiMa.ai on the launch of Modalix™ - a next-generation MLSoC, designed to deliver impressive AI performance and energy efficiency at the edge. | Arm

Congratulations to SiMa.ai on the launch of Modalix™ - a next-generation MLSoC, designed to deliver impressive AI performance and energy efficiency at the edge. Modalix™ is built on the Arm compute platform - enabling real-time perception, decision-making, and natural language interaction and...

www.linkedin.com

 

[Frangipani]

I remember having seen Gabriela Mystkowska in a photo taken in the BrainChip private room at some trade fair. She was part of a group visiting BrainChip. I can't remember the other people, though. As far as I remember, the picture was marked as "our partners XX" and changed or deleted later, probably because of the mistake that she was not part of the partner group.

But maybe I am mistaken, maybe it was some other lady, though I immediately remembered her when I saw this photo.

Hi @CHIPS,

I think you’re confusing Gabriela Mystkowska, who is a Polish PhD student at the University of Pisa’s Department of Information Engineering as well as a Visiting Researcher at ESA (which also happens to be the organisation that is co-funding her PhD), with Sylvia Traxler, who is a Senior Principal Software Engineer at Raytheon Technologies.

https://www.linkedin.com/in/gabriela-mystkowska/

Sylvia Traxler - Raytheon Technologies | LinkedIn

Experience: Raytheon Technologies · Education: The University of Texas at Austin · Location: Greater Tampa Bay Area · 448 connections on LinkedIn. View Sylvia Traxler’s profile on LinkedIn, a professional community of 1 billion members.

www.linkedin.com

Sylvia Traxler was one of three RTX employees visiting the BrainChip private suite at the Venetian Tower during CES 2025. We know that to be a fact, since she and her colleagues Bryce Nakamori and Geoff Martin were featured in a group photo together with Steve Thorne and JP Wright, which was later posted by BrainChip on LinkedIn. However, that “Day 2: Productive Day at #CES2025” post publicly revealing RTX as a BRN partner vanished into thin air shortly after.

Some of us had long figured out that RTX were likely the subcontractor in question with regards to the AFRL SBIR contract that BRN had been awarded in December 2024, but apparently the negotiations were either not completely cut and dried or there were other reasons why this partnership was not yet supposed to go public. Anyway, IMO a very unprofessional slip-up to completely delete a publicly visible LinkedIn post without a comment. They could have just edited it instead.

Here are several 9 January 2025 posts by @Tothemoon24, @miaeffect, @Quiltman and @SERA2g, which prove that the LinkedIn post in question did exist for a short time - unfortunately, no one that day appears to have posted the actual picture showing the RTX trio…

 

[Mazewolf]

Some weekend musings, assisted by copilot and grok...
.
### Could the Development of These Cryptocurrencies Drive Adoption of Neuromorphic Edge Products?

Yes, the ongoing development of QRL, IOTA, Dynex (DNX), Bittensor (TAO), and Hedera (HBAR) has strong potential to accelerate the adoption of neuromorphic edge products. Neuromorphic edge computing involves hardware and software that emulate the brain's neural structures for efficient, low-power AI processing directly on devices (e.g., sensors or IoT gadgets), reducing latency and energy use compared to traditional cloud-based systems. These cryptocurrencies foster ecosystems that demand such capabilities—through decentralized computing, AI incentives, IoT integration, and quantum-secure infrastructures—creating economic and technical incentives for neuromorphic hardware deployment. This could mirror how blockchain has driven GPU adoption for mining, but shifted toward brain-inspired chips for edge AI.

Here's how each cryptocurrency could contribute:

- **Dynex (DNX)**: As a neuromorphic quantum computing platform, Dynex directly integrates brain-like algorithms into its blockchain for decentralized supercomputing. Its cloud-based model allows users to access neuromorphic resources for tasks like AI simulations and pattern recognition, lowering barriers to entry and incentivizing hardware providers to build compatible edge devices. This could drive widespread adoption by making neuromorphic computing economically viable for real-world applications, with partnerships and educational programs further promoting integration

- **Bittensor (TAO)**: Bittensor's decentralized AI marketplace rewards machine learning contributions, which could extend to neuromorphic hardware for energy-efficient edge training and inference. Synergies with neuromorphic systems (e.g., spiking neural networks) enable real-time AI on devices, driving adoption in robotics and healthcare by incentivizing developers to optimize for low-power edge setups.

- **IOTA**: Designed for IoT, IOTA's feeless, scalable Tangle architecture aligns perfectly with neuromorphic edge devices for secure, real-time data processing in distributed networks. By enabling machine-to-machine economies, it could spur neuromorphic integration in IoT sensors and edge AI, addressing energy constraints and security needs, thus accelerating adoption in smart cities and industrial applications.>

- **Hedera (HBAR)**: Hedera's high-throughput, enterprise-grade network supports DePIN (decentralized physical infrastructure networks) like drone radar systems, which could incorporate neuromorphic chips for efficient edge processing. While less directly tied, its focus on secure, scalable AI and IoT applications could indirectly boost neuromorphic adoption through partnerships in healthcare and autonomous systems.

- **QRL**: As a quantum-resistant ledger, QRL ensures secure transactions in a post-quantum world, protecting neuromorphic edge data from threats. While not neuromorphic-specific, its emphasis on long-term security could enable safe deployment of brain-inspired devices in sensitive edge environments, indirectly supporting adoption as quantum-neuromorphic hybrids emerge.

Broader trends support this: Cryptocurrencies like these are already intersecting with neuromorphic tech for energy-efficient blockchain operations, edge AI, and DePIN, with market projections showing neuromorphic growth to $1.3 billion by 2030, driven by AI/ML demands.

Recent discussions highlight crypto's role in onboarding users to neuromorphic ecosystems, though challenges like hardware standardization remain.

### Likely Candidates for the Type of Neuromorphic Edge Products

Based on 2025 trends, neuromorphic edge products will focus on low-power, real-time AI in decentralized and IoT-heavy environments. These cryptocurrencies could catalyze development by providing token incentives, secure networks, and computational marketplaces. Here are key candidates:

- **Autonomous Vehicles and Drones**: Neuromorphic chips enable on-device pattern recognition for navigation and obstacle avoidance, with low energy for extended flights/rides. IOTA and HBAR's IoT/DePIN focus could drive this, as seen in drone radar trials.

- **Smart Sensors and IoT Devices**: Energy-efficient sensors for environmental monitoring or industrial automation, processing data locally. Dynex and IOTA ecosystems could incentivize neuromorphic integration for secure, scalable DePIN networks.

- **Wearable Health Monitors**: Devices like smartwatches with on-device diagnostics for real-time health tracking. TAO's AI incentives and Dynex's efficient computing could promote neuromorphic chips for privacy-focused, low-power monitoring.

- **Edge AI Robotics**: Robots with brain-inspired processing for adaptive learning in manufacturing or homes. Bittensor's ML sharing and QRL's security could ensure safe, decentralized control, boosting neuromorphic hardware like add-ons for Raspberry Pi.

- **Security Cameras and Vision Systems**: Cameras with on-device object detection for privacy-preserving surveillance. Neuromorphic efficiency suits edge demands, with cryptocurrencies like IOTA and HBAR enabling secure data sharing in smart cities.

These products align with 2025 forecasts emphasizing federated learning, spiking neural networks, and integration with AI clouds, potentially reaching billions of devices. However, success depends on overcoming scalability hurdles and regulatory alignment—crypto volatility could hinder, but utility-driven growth might prevail.