ArtGonzo
Observer
Whales are coming.
Whales are coming.
I wonder if was Sean/Brainchip that reached out to SDU for an interview so they can update the market, without actual updating on the market,He looks and sounds confident for this success
At the 1.20 mark he mentioned his thoughts for this year is still in the cards.I wonder if was Sean/Brainchip that reached out to SDU for an interview so they can update the market, without actual updating on the market,
Personally, I unfortunately don’t have access to current charts or buy and short data. It’s always helpful when people like you share the current situation. Sometimes, it’s hard to understand the price movements without having the data… Thanks for that.Afternoon Chippers ,
Around this time yesterday we saw a little step up in price & volume , looking at the trading string presently seeing a lot of Bull $hite trades .
Oh , & yesterday some tosser took out 5 mill share short , good luck with that .
Regards,
Esq.
At the 1.20 mark he mentioned his thoughts for this year is still in the cards.
I think you are correct, he is telling us something positive here imo .
Early Christmas present , fingers crossed.
Looking like the market didn;t like it. 2024 just became 2025.At the 1.20 mark he mentioned his thoughts for this year is still in the cards.
I think you are correct, he is telling us something positive here imo .
Early Christmas present , fingers crossed.
Don’t think so2025 now...
What happened to deals by the end of 2024?
Looking like the market didn;t like it. 2024 just became 2025.
Groundhog day....
FiveBucks ..,Listen again at 1.20 mark
View attachment 72499
Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.
Hi Dio ,"random stimulus" suggests an uncontrolled environment.
I wonder if it is a pointer for ADAS/AV, UAVs?
Of course there are many other applications which could be subject to random inputs, but ...
The ad is for a hardware verification engineer, so some new silicon is probably in the pipeline.
I assume that doesn't mean we will be going back to commerial chip-making, but we will be developing FPGAs and possibly "engineering samples" of the real hardware.
The job is apparently in India, where we do software, so will the softwarel be tested on silicon designed by BRN in the US, or will it be tested on 3rd party CPUs/GPUs? As it is a hardwaew verification position, I'm betting on BRN hardware.
... but of course we have a newish algorithm product (TENNs/Akida simulation?), and TENNs is undergoing ongoing development and will run on 2rd party hardware.
... more questions than answers.
Do we know if this job is for a one-off time-limited contract or full time?
Why has the poster asked people to reply to a gmail address rather than a Brainchip email address??View attachment 72499
Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.
MB getting ready for their latest Town Hall meeting, with focus on MB.OS.
As we approach the end of an incredible year, it’s time for me to get ready for our latest “town hall“ meeting. This one focuses on MB.OS and I couldn’t be more excited! We’ll be gathering as a team to reflect on our major milestones, share updates, and set our sights on a strong finish for 2024.
Sounds like a job for ChapmanView attachment 72499
Hi Everyone,
We're hiring for Design Verification position with below skills.
Qualifications:
1. B.Tech. with 6-8 years/ M.Tech. with 5-7 years of relevant experience.
2. Experience in verification of complex IPs/units and sub-systems.
3. Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies.
4. Knowledge in SystemVerilog or similar HVL.
5. Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug.
6. Experience with System Verilog Assertion (SVA) a plus.
7. Experience with Perl, Python or other scripting language is a plus
8. Experience with Industry Standard protocols like I2C/SPI/GPIO/AXI/APB/AHB is a plus.
9. Must have done atleast one project from scratch in SV/UVM.