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Q&A with SiFive SVP Jack Kang: 5 nm chips with SiFive cores likely to be used in cars by 2025-2026

Judy Lin, DIGITIMES Asia, Taipei
Wednesday 21 September 2022
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Credit: DIGITIMES

SiFive successfully rolled out a portfolio of automotive CPUs based on the RISC-V standard, and is about to create a new ecosystem of chips, tier-1 auto component providers and OEM partners. DIGITIMES had an exclusive interview with SiFive SVP Jack Kang, who shared what triggered the RISC-V leader's entry into cartech chip IP and the new opportunity SiFive's new portfolio is creating for the supply chain.

Q: What makes the new portfolio stand out from the IP currently available on the market?

We've seen tremendous growth for RISC-V in all market segments over the last few years, and it keeps growing. Automotive is one area where there's a lot of interest now. Why? Because the automotive ecosystem is changing, it's evolving. There's a whole new software ecosystem. A lot of customers have what's called "first party software", which means they're in control of their own software stacks. That means it's easy for them to move to new architectures, especially when that architecture bring significant benefits in power performance, ecosystem choice and things of that nature.

In the RISC-V space, SiFive has the most complete portfolio of products for automotive. There are some other options by vendors who have announced certain point products, but in the RISC-V space this is the most complete portfolio of products for automotive, in terms of supporting everything from 32 bit to 64 bit to vector processing, covering all the different areas for the automotive market. The strength of SiFive is that we're able to provide the entire portfolio. There are multiple different cores within a system, and there are multiple different SOCs, which all need different versions of a CPU. Being able to provide that is very critical for large-scale adoption. Then you get the specific benefits offered by the RISC-V ecosystem combined with the benefits offered by SiFive products. From an ecosystem standpoint, by moving your software to RISC-V you now have freedom of choice. You have lots of open-source software developers working on it, and you're going to have different suppliers offering solutions.

The RISC-V ecosystem is going to grow much faster, and you're not dependent on any one vendor, which means you're going to have more diversity of choices. Then you look at the SiFive products themselves. Our products provide significant power and area advantages at the same performance level as other cores. If you compare to other competing cores from suppliers like ARM and others, SiFive typically offers 30 to 40% better power consumption efficiency, plus a smaller area. This enables more cores on a chip, a lower cost for chips, and lower power consumption.

Q: Besides Renesas, which companies have become partners with SiFive in their new products? Do your IP also have to go through years of validation with the auto makers?

On the open-source point, it's very important to understand that RISC-V is an open standard. That open standard is shared, which means lots of people can do things on it, enabled by a community of openness. And with that there's a lot of open-source software developed for RISC-V. There's a significant ecosystem of partners who develop software; high integrity, fault tolerant software for the automotive space. Now, those are not open source, right? Those partners are crucial partners for the day-to-day grind. By supporting RISC-V, then their ecosystem of hardware partners expands to not just SiFive, but others. This is why RISC-V is mutually beneficial, and there'll be large-scale adoption.

For the partners in our ecosystem, Renesas, along with some 15 other companies, announced support for our automotive launch. We have a couple of other very large customers, tier-1 chip companies, but they are not public, so you have to look for those announcements in the weeks and months to come. But we do have customers for all of these products that we are announcing today.

Our IP is very thoroughly validated on the baseline stuff, and then when we get into the automotive products, there are certain SOP/SOD type of requirements and compliance things that are required.

In many cases, either we're providing those, or we're working with our customers closely to ensure that the solutions meet safety and reliability standards. Because if we look at the automotive space, ultimately, it's about the safety and quality requirements for the final end product and for the system level. So it depends on the customer: some of it is deployed at the system level, some of its deployed in the chip level, some of it is deployed in the IP level. You'll see in the release that we talked about our products being capable and suitable for different types of applications.

SiFive has been around for seven years now. Some of our automotive products have their roots in the success of other embedded products shipping with our IP. It's hard for me to quantify how many years of verification we do for each one, but as IP providers, it is very important that we build and develop trust with our customers.

Q: What inspired SiFive to make entry to the Cartech space? How many years of R&D have you spent in it?

Actually, it was our customers that kept asking us. A couple years ago, we were a little bit hesitant. We were working in other areas, and they kept asking. There's clearly a demand here and a need for something.

Cars have been going through this very rapid technology change. With the electrification of cars and cars becoming a "data center on wheels," cars are becoming very advanced technically. But if you look at semiconductors and the CPU IP available for the space, it has not made the same progress as CPUs and chips for AI or data center chips or mobile chips. The automotive space was a little bit behind, so there was an opportunity for innovation to come in.

Our customers kept pushing until finally we decided we had to take on this market opportunity. And the more we looked into the automotive space, the more we discovered that it is a very good fit for our products and our roadmap, not just the three new solutions that we announced. And we've built a team of automotive experts to help drive this forward.

Q: Which process nodes best suit E6-A, S7-A and X280-A series of processors?

It's pretty broad because we have customers in every automotive node you can think of because RISC-V is very flexible. Now, as you get to higher and higher performing cores, and you start talking about more advanced capabilities, such as ADAS, and you get to L-3, L-4 and beyond, those chips are going into more and more advanced processes because you still need that processing capability.

That creates some additional challenges for functional safety and fault tolerance and has to be handled in other ways. For some of the other functions, maybe they will stay at some of the older nodes. As you get to the higher and higher performance ones and the more advanced nodes, you're going to be pushing into higher and higher performance cores. Some of that will probably be the cores on our roadmap that we haven't announced yet, that will be pushing towards 5 nm or lower nodes because you need that kind of compute.

Q: How long would it take for that core to go into five or below 5 nm?

The auto industry is speeding up, but it still has a longer cycle than consumer or mobile or even the datacenter. For the discussions that we're having now, our IP will be used for chips in 2024 and 2025, which means they won't make it into cars until the model years 2025 or 2026. Right now, they're all trying to accelerate that schedule. That's probably the fastest timeframe that you'd be looking at. It's not like mobile, where you announce something and you see it right away.

Q: And because cybersecurity is the issue that many people concerned about the connected vehicles, how secure is the RISC-V architecture auto processors?

Security is a system issue. One of the very things about RISC-V is from an architecture standpoint, it was developed at a time when cyber security is very important. RISC-V has a clean slate, no legacy of stuff that you're trying to attach onto it. For example, Spectre and Meltdown happened a couple of years ago, but no RISC-V cores were affected by that.

SiFive offers a security model called WorldGuard. This is an example of a security implementation our customers can choose. And there is an advantage to being built on RISC-V also. RISC-V is an open standard, that means its architecture is available for everybody to see. You get the benefit of all of the companies looking at it, and making sure there are no issues and holes, and contributing to the shared standard. At the end, you still have to do the right thing, not just in the CPU, IP, but also in the SOC and the system. Everybody has to pay attention to it. The good news is that security requirements are down to the core, and people have a much better understanding compared to even five years ago or 10 years ago. That's a big advantage that SiFive has: a clean slate for designs.

Q: Intel has this collaboration with you and also with the RISC-V community. The foundry service for all those chips will go to Intel? Or other foundry makers also have a chance.

Intel has certainly been a big proponent for RISC-V, which is great for the ecosystem. They see that this is where a lot of new chip designs are going to happen, and RISC-V will drive value for their foundry. You're going to see this across the board, all foundries are going to benefit from more RISC-V designs. This is where the foundries get to differentiate on their capabilities and features. We'll see how they compete, but it's clear that RISC-V is going to create more opportunities for all the foundries.
 
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SiFive’s New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products

Next generation P670 and P470 RISC-V Processors bring ultimate flexibility and balance of performance and efficiency for next-generation wearables and smart consumer devices

Santa Clara, Calif., November 1, 2022 - SiFive, Inc. the founder and leader of RISC-V computing, today announced two new products that address the need for high performance and efficiency in a small size in high volume applications like wearables, smart home, industrial automation, AR/VR, and other consumer devices. The SiFive Performance™ P670 and P470 RISC-V processors bring unparalleled compute performance and efficiency that is significantly raising the bar for innovative designs in these high-volume markets. The modern and innovative SiFive design methodologies bring raw compute density that is a substantial advantage for SiFive Performance products and also translates into significant cost savings for customers.

“The P670 and P470 are specifically designed for, and capable of handling the most demanding workloads for wearables and other advanced consumer applications. These new products offer powerful performance and compute density for companies looking to upgrade from legacy ISAs,” said Chris Jones, SiFive VP of Product. “We have optimized these new RISC-V Vector enabled products to deliver the performance and efficiency improvements the industry has long been asking for, and we are in evaluations with a number of top-tier customers. Additionally, as the upstream enablement of RISC-V has started within the Android Open Source Project, (AOSP), designers will have unrivaled choice and flexibility as they consider the positive implications with that platform for future designs.”

"We are excited to see RISC-V solutions for wearable and consumer devices becoming a reality, and we are looking at possibilities of integrating SiFive’s latest products into Snapdragon platforms,” said Ziad Asghar, Vice President, Product Management- Snapdragon Technologies and Roadmap at Qualcomm.

"Samsung’s System LSI Business holds a wide portfolio of solutions for various applications, such as mobile, wearables and other consumer devices. We look forward to evaluating how the latest RISC-V innovations from SiFive can enhance our offerings,” said Jinpyo Park, VP of the Innovative AP Development Team, Samsung Electronics System LSI Business.

“SiFive continues to be a market leader in the growing and maturing RISC-V space and again shows its leadership with its new SiFive Performance P670 and P470 RISC-V processors,” said Todd R. Weiss, an analyst with Futurum Research. “These latest and powerful new processors give SiFive feature and performance advantages that will gain plenty of attention from device makers and consumers who want more from their devices. SiFive has been growing its reputation for some time and is truly ready to shake up the marketplace.”

Features

The SiFive Performance P470 and P670 products offer a finely-tuned combination of compute-density, power efficiency, and robust feature sets ideal for a wide range of applications and markets:

• Support for virtualization, including a separate IOMMU for accelerating virtualized device IO

• Full, Out-of-Order, RISC-V Vector implementation, based on the ratified RISC-V Vector v1.0 Specification

• First to market with the RISC-V Vector Cryptography extensions

• SiFive WorldGuard system security

• Full RISC-V RVA22 profile compliance

• New, Advanced Interrupt Architecture (AIA) compliant interrupt controller, with better support for Message Signal Interrupts (MSI) and virtualization

• Enhanced scalability with fully coherent multi-core, multi-cluster, with support for up to 16 cores

SiFive Performance P670

The P670 is ideal for applications like premium wearables, networking, robotics, and mobile. The P650, which excludes the vector unit, is already shipping to lead customers and is being used in applications that do not require the additional capabilities that vector compute offers or are more area constrained.

The feature rich P670:

• achieves a maximum frequency exceeding 3.4GHz in 5nm,

• has performance of greater than 12 SpecINT2k6/GHz, offering optimized performance in a constrained area and power envelope,

• offers higher single threaded performance and 2x compute density compared to legacy solutions, and

• includes a 2x 128-bit Vector ALUs compliant with the ratified RISC-V Vector v1.0 specification

SiFive Performance P470

The P470 is SiFive’s first efficiency-focused Out-of-Order, area optimized, vector processor, ideal for applications like wearables, consumer, and smart home devices. Expanding on the proven P500-Series, the P470 is significantly smaller than competing solutions and optimized to have best-in-class performance efficiency and area density. The P470 was designed to also serve as a companion to the P670 processor for demanding applications that require a sharing of compute resources while optimizing power consumption.

The P470 offers a significant upgrade to legacy efficiency cores, achieving a maximum frequency exceeding 3.4GHz in 5nm, and greater than 8 SpecINT2k6/GHz, within a minimal area and power envelope.

Other P470 features include:

• 4x compute density in comparison to leading competitor

• Includes 1x 128-bit RISC-V Vector ALU compliant with the ratified RISC-V Vector v1.0 specification

SiFive will also release the P450 – an area-optimized version of the P470 that excludes the Vector Unit.

A presentation highlighting the benefits of the new products will be made at the Linley Fall Microprocessor Conference later today.

For more information on SiFive’s market-leading RISC-V IP portfolio, please visit SiFive.com/risc-v-core-ip.
 
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Deadpool

hyper-efficient Ai

Informative video, but isn't it funny when things don't go to plan during presentation, we are in the most technological advanced time in history yet we still have problems with the little things, Power Point page timing issues and bandwidth problems, that make the pro's look complete armatures sometimes.
Not to mention the Cyber truck debacle.:ROFLMAO:
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cosors

👀
Naveed getting the BrainChip name out to his 36,356 followers

View attachment 4945


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RISC-V companies SiFive, Esperanto Technologies, Inc and others continue their march on AI related workloads.

The other day, we reported on Esperanto Technologies, Inc chip bring up, today we report on news from SiFive .


SiFive and BrainChip Partner to Demo IP Compatibility

By Sally Ward-Foxton


SiFive and BrainChip have partnered to show their IP is compatible in SoC designs for embedded artificial intelligence (AI). The companies have demonstrated BrainChip’s neuromorphic processing unit (NPU) IP working alongside SiFive’s RISC–V host processor IP.

Brainchip’s NPU processor IP, the basis for its Akida chip, is a neuromorphic processor designed to accelerate spiking neural networks. This IP can be used to analyze inputs from most sensor types, including cameras, to provide ultra–low power analysis in real–time applications. A recent BrainChip demo showed its Akida chip in a vehicle, detecting the driver, recognizing the driver’s face, and identifying their voice simultaneously. Keyword spotting required 600 µW, facial recognition needed 22 mW, and the visual wake–word inference used to detect the driver was 6–8 mW.

SiFive is a provider of RISC–V processor IP, including its Intelligence series of multi–core capable RISC–V processors with vector extensions which are optimized for AI workloads in edge devices.

“BrainChip can run [AI] algorithms on their own, but when they move into a larger system, they will need a host processor,” Chris Jones, vice president, product at SiFive, told EE Times. “You could pick a host processor that does nothing but scheduling, or you could pick a host processor that actually contributes to the AI processing, and that’s where the SiFive Intelligence product comes in.”

In an SoC design for edge AI, the AI workload would typically be split between host processor, vector processor, and AI accelerator — some parts of edge workloads are better suited to general purpose compute rather than a dedicated AI accelerator, Jones said.

“It’s advantageous for BrainChip to align with industry leaders to make sure their customers have a seamless integration experience, so BrainChip can deliver the requisite software that runs on the host processor and makes it easier for the end user to integrate their products and ours,” he said.

Details:
I am replying to your old post as Dr Naveed Sherwani gives just few hits here on TSE.
And your post I find interesting as it shows that he knows Akida. He was President and CEO of SiFive and has now been appointed Non-Executive Director of MosChip in June which the company seems to be very proud of.
Who knows, maybe we'll hear from MosChip again sometime.

"MosChip Announces the appointment of Semiconductor Industry Veteran Dr. Naveed Ahmed Sherwani to the Board of Directors​

by Semiconductor For You June 19, 2023 in Semiconductor News

Santa Clara, CA, – June 19, 2023 – MosChip Technologies, a semiconductor and system design servicescompany, announced that Dr. Naveed Sherwani has been appointed as “Non-Executive Director” of the Company.

1697016501858.png


Dr. Sherwani has decades of experience in entrepreneurship, technical engineering and general management. Dr. Sherwani currently serves as Chairman, President and CEO of RapidSilicon, a leading FPGA company, in addition to serving on multiple boards and advisor to several companies.


Prior to this role, he served as chairman, president and CEO of SiFive, a leader in RISC-V. He also serves as chairman of several companies, including StarFive and LeapFive. In addition, he served as chair, RISC-V strategic alliances at RISC-V international.


Dr. Sherwani started his first company, when he was only 18 years old. He has founded and co-founded multiple companies. Prior to joining SiFive, he founded PeerNova, a company focused on technology solutions Based on blockchain technology. Dr. Sherwani served as Chairman, President and CEO of PeerNova.


Prior to PeerNova, Dr. Sherwani co-founded Open-Silicon, a leading provider of ASIC solutions. Under his leadership, Open-Silicon designed over 300 ASICs. Prior to Open Silicon, as the founder and General Manager of Intel Microelectronics Services, he pioneered Open methodology for ASICs. He also founded Brite Semi, a leading ASIC solution provider in China/APAC.


He has served on the boards of various companies, including Touchstone Semiconductor, and Integration associates (sold to Silicon Labs). Dr. Sherwani worked at Intel for nearly a decade, where he co-architected the Intel microprocessor design methodology and design environment used in several microprocessors and received the prestigious Intel achievement Award in 1997.


Dr. Sherwani is a noted author having authored several books and over 100 articles on various aspects of VLSI Physical Design Automation and ASICs. Dr. Sherwani served as a Professor at Western Michigan University, where his research focused on ASICs, EDA, Combinatorics, graph algorithms and parallel computing. He received his Ph.D. from the University of Nebraska-Lincoln.

“MosChip has made significant progress in both Semiconductor and Embedded product development services and looking at expanding our foot print in turn-key ASIC and ASSP development. We are very excited to have Dr. Naveed Sherwani on our board as his track record and knowledge will be a huge help in formulating our strategy and expansion” said, MosChip’s MD and CEO, Mr. Venkata Simhadri."
https://www.semiconductorforu.com/m...eed-ahmed-sherwani-to-the-board-of-directors/

MosChip Announces the appointment of Semiconductor Industry Veteran Dr. Naveed Sherwani to the Board of Directors - 19th June 2023


In the meantime, TSE has grown into a good database, so I would like to archive this piece of the puzzle or this person and connection here.
 
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